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| CCD Delay Line Series MN3881S PAL-Compatible CCD Video Signal Delay Element Overview The MN3881S is a CCD signal delay element for video signal processing applications. It contains such components as a shift register clock driver, charge I/O blocks, 1/2nd frequency doubler, two switchable CCD analog shift registers, a clamp bias circuit, resampling output amplifiers, a mode selection circuit and booster circuits. When the switch pin is grounded, the MN3881S samples the input using the supplied clock signal with a frequency 8.8672375 MHz of twice the PAL color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the PAL system) for the Y output and 2 H for the C output. Pin Assignment VBIASC VOC N.C. VDD -VBB N.C. VOY VBIASY 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VINC N.C. N.C. XI VSS SW N.C. VINY Features Single 4.9 V power supply Single chip combining luminance signal delay element and delay element for color signal converted to low frequency. ( TOP VIEW ) SOP016-P-0225 Applications VCRs 1 MN3881S Block Diagram CCD Delay Line Series 12 4 Auto bias circuit VINC 16 Charge input block Charge detection block CCD 567 stages Resampling output 2 amplifier 1 VBIASC VDD VSS VOC oS driver o1 driver o2 driver oR driver oSH driver oSH driver Timing adjustment XI 13 Waveform amplifier adjustment block 1/2nd frequency doubler Timing adjustment oS driver o1 driver o2 driver oR driver oSH driver oSH driver Auto clamp circuit VINY 9 Charge input block 5 CCD 566.5 stages 11 Charge detection block Resampling output 7 amplifier VOY -VBB SW 2 VBIASY 8 CCD Delay Line Series Application Circuit Example 10F -+ VBIASC MN3881S 0.01F 12 VSS 0.1F 4 VDD Auto bias circuit VINC 16 0.01F Charge input block Charge detection block CCD 567 stages Resampling output 2 VOC amplifier oS driver o1 driver o2 driver oR driver oSH driver oSH driver Timing adjustment XI 13 1000pF Waveform amplifier adjustment block 1/2nd frequency doubler Timing adjustment oS driver o1 driver o2 driver oR driver oSH driver oSH driver Auto clamp circuit VINY 9 -+ 0.47F Charge input block 5 1 CCD 566.5 stages SW 11 Charge detection block Resampling output amplifier 7 VOY 0.01F VBIASY 8 -VBB 0.01F Note: If the capacitor attached to pin 5 has a polarity, attach the negative pole to pin 5. 3 MN3881S Package Dimensions (Unit:mm) SOP016-P-0225 CCD Delay Line Series 10.100.20 16 9 1.100.20 4.300.20 6.500.20 1 8 1.500.20 +0.50 -0.20 0.15 -0.05 +0.10 0 to 10 0.40min. (0.6) 1.27 0.400.10 SEATING PLANE 4 0.100.10 1.60 |
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